The present invention relates to integrated circuit devices and, more particularly, to ferroelectric integrated circuit devices, such as memory devices, and methods for operating the same.
Recently, ferroelectric memory devices using ferroelectric layers have been considered as an alternative approach for certain memory applications. Ferroelectric memory devices are generally divided into two categories. The first category includes devices using a ferroelectric capacitor as described, for example, in U.S. Pat. No. 5,523,964. The second category includes devices having a ferroelectric field emission transistor (FET) as described, for example, in U.S. Pat. No. 5,198,994. Ferroelectric memory devices generally use polarization inversion and remnant polarization characteristics of an included ferroelectric layer to provide desired properties to the memory devices. These devices may provide higher-speed read and write operations and/or lower power consumption than other types of memory devices.
Because polarization inversion of a ferroelectric layer results from rotation of a dipole, ferroelectric memory devices may have an operation speed over 100 times faster than other nonvolatile memory devices, such as Electrical Erasable Programmable Read Only Memory (EEPROM) devices or flash memory devices. In addition, with optimized designs, ferroelectric memory devices may result in write operation speeds ranging from several hundreds of nanoseconds to several tens of nanoseconds. Such high speed operations may even be comparable to the operating speed of Dynamic Random Access Memory (DRAM) devices. With respect to possible power savings, EEPROM or flash memory devices typically require use of a high voltage of about 18 volts (V) through about 22 V for a write operation. Ferroelectric memory devices generally only need about 2 V through about 5 V for polarization inversion. Accordingly, they may be designed to operate with a single low-voltage power supply.
Ferroelectric memory cells generally store a logic state based on electric polarization of a ferroelectric capacitor as noted above. The ferroelectric capacitor typically has a dielectric material that includes a ferroelectric material, such as lead zirconate titanate (PZT). When voltages are applied to both electrodes (or plates) of a ferroelectric capacitor, the ferroelectric material is generally polarized in the direction of the resulting electric field. The switching threshold for changing the polarization state of the ferroelectric capacitor is sometimes called a coercive voltage.
A ferroelectric capacitor typically exhibits a hysteresis characteristic. Current generally flows into a ferroelectric capacitor based on its polarization state. If a difference voltage between the electrodes of the ferroelectric capacitor is higher than the coercive voltage, the polarization state of the ferroelectric capacitor may be changed based on the polarity of a voltage applied to the ferroelectric capacitor. The capacitor's polarization state is generally maintained even after power-off, thus providing a ferroelectric memory device with a non-volatile characteristic. The ferroelectric capacitor may vary between polarization states in approximately 1 nanosecond. Thus, a device may be provided having a faster program time than non-volatile memories such as EPROMs and flash EEPROMs.
FIG. 1 illustrates a ferroelectric memory cell having a conventional one transistor/one capacitor (1T/1C) structure. A ferroelectric memory cell MC is provided having one switching transistor Tr and one ferroelectric capacitor Cf. One current electrode of the switching transistor Tr is connected to a bit line BL, and the other thereof is connected to a plate line PL. As illustrated in FIG. 1, a voltage Vp that is applied to the plate line PL. The voltage Vf is a division voltage (or a coupling voltage) between both electrodes of the ferroelectric capacitor Cf. The voltage Vf corresponds to the bit line voltage.
Read and write operations for such a ferroelectric memory device can be carried out by applying a pulse signal to a plate line PL connected to the ferroelectric capacitor Cf. As the ferroelectric capacitor generally has a high permittivity, the ferroelectric capacitor Cf may have a high capacitance. Furthermore, as a large number of ferroelectric capacitors are commonly connected to one plate line, a pulse signal applied to the plate line may have a long delay time (and/or a long rising time). Such a long delay time may reduce the operating speed of a ferroelectric memory, however, such a result may be unavoidable given the structure of a ferroelectric memory device. To increase the operating speed of the ferroelectric memory device, changes to the control logic other than adjusting the delay time of a pulse signal applied to the plate line may be desired when the delay time limitation is reached.